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74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
January 2008
74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable
Features
ICC reduced by 50% Ideal for addressable register applications Clock enable for address and data synchronization
General Description
The AC/ACT377 has eight edge-triggered, D-type flipflops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
applications Eight edge-triggered D-type flip-flops Buffered common clock Outputs source/sink 24mA See 273 for master reset version See 373 for transparent latch version See 374 for 3-STATE version ACT377 has TTL-compatible inputs
Ordering Information
Order Number
74AC377SC 74AC377SJ 74AC377MTC 74ACT377SC 74ACT377SJ 74ACT377MTC 74ACT377PC
Package Number
M20B M20D MTC20 M20B M20D MTC20 N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard.
FACTTM is a trademark of Fairchild Semiconductor Corporation. (c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
Connection Diagram
Pin Descriptions
Pin Names
D0-D7 CE Q0-Q7 CP Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input
Description
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs Operating Mode
Load `1' Load `0' Hold (Do Nothing) X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
Outputs Dn
H L X X
CP
CE
L L H H
Qn
H L No Change No Change
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 2
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 3
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC IIK Supply Voltage DC Input Diode Current VI = -0.5V VI = VCC + 0.5V VI IOK DC Input Voltage DC Output Diode Current VO = -0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage
Parameter
Rating
-0.5V to +7.0V -20mA +20mA -0.5V to VCC + 0.5V -20mA +20mA -0.5V to VCC + 0.5V 50mA 50mA -65C to +150C 140C
DC Output Source or Sink Current Storage Temperature Junction Temperature
ICC or IGND DC VCC or Ground Current per Output Pin
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC Supply Voltage AC ACT VI VO TA V / t V / t Input Voltage Output Voltage Operating Temperature
Parameter
Rating
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125mV/ns 125mV/ns
Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 4
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
DC Electrical Characteristics for AC
Symbol
VIH
Parameter
Minimum HIGH Level Input Voltage
VCC (V)
3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5
TA = +25C Conditions
VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50A
TA = -40C to +85C Guaranteed Limits Units
V 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 75 -75 A mA mA A V V V
Typ.
1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1
3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86
VIL
Maximum LOW Level Input Voltage
VOH
Minimum HIGH Level Output Voltage
VIN = VIL or VIH, IOH = -12mA VIN = VIL or VIH, IOH = -24mA VIN = VIL or VIH, IOH = -24mA(1) 0.002 0.001 0.001 VIN = VIL or VIH, IOL = 12mA VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL = 24mA(1) VI = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND IOUT = 50A
VOL
Maximum LOW Level Output Voltage
3.0 4.5 5.5 3.0 4.5 5.5
0.1 0.1 0.1 0.36 0.36 0.36 0.1
IIN(3) IOLD IOHD ICC
(3)
Maximum Input Leakage Current Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current
5.5 5.5 5.5
4.0
40.0
Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 5
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
DC Electrical Characteristics for ACT
Symbol
VIH VIL VOH
Parameter
Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage
VCC (V)
4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5
TA = +25C Conditions
VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50A VIN = VIL or VIH, IOH = -24mA VIN = VIL or VIH, IOH = -24mA(4) IOUT = 50A VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL = 24mA(4) VI = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND 4.0 0.6 0.001 0.001 4.86 0.1 0.1 0.36 0.36 0.1
TA = -40C to +85C Units
V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 40.0 A mA mA mA A V
Typ.
1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4
Guaranteed Limits
3.86
VOL
Maximum LOW Level Output Voltage
4.5 5.5 4.5 5.5
IIN ICCT IOLD IOHD ICC
Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(5) Maximum Quiescent Supply Current
5.5 5.5 5.5 5.5
Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time.
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 6
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
AC Electrical Characteristics for AC
TA = +25C Symbol
fMAX tPLH tPHL
TA = -40C to +85C Min.
75 125 13.0 9.0 13.0 10.0 1.5 1.5 2.0 1.5 14.0 10.0 14.5 11.0 ns ns
Parameter
Maximum Clock Frequency Propagation Delay, CP to Qn Propagation Delay, CP to Qn
VCC
(V)(6)
Min.
90 140 3.0 2.0 3.5 2.5
Typ.
125 175 8.0 6.0 8.5 6.5
Max.
Max.
Units
MHz
3.3 5.0 3.3 5.0 3.3 5.0
Note: 6. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V
AC Operating Requirements for AC
TA = +25C, CL = 50pF Symbol
tS tH tS tH tW
TA = -40C to +85C, CL = 50pF Guaranteed Minimum Units
ns ns ns ns ns 6.0 4.5 0 1.0 7.5 4.5 0 1.0 6.0 4.5
Parameter
Setup Time, HIGH or LOW, Dn to CP Hold Time, HIGH or LOW, Dn to CP Setup Time, HIGH or LOW, CE to CP Hold Time, HIGH or LOW, CE to CP CP Pulse Width, HIGH or LOW
VCC (V)(7)
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Typ.
3.5 2.5 -2.0 -1.0 4.0 2.5 -3.5 -2.0 3.5 2.5
5.5 4.0 0 1.0 6.0 4.0 0 1.0 5.5 4.0
Note: 7. Voltage range 3.3 is 3.0V 0.3V. Voltage range 5.0 is 5.0V 0.5V
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 7
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
AC Electrical Characteristics for ACT
TA = +25C, CL = 50pF Symbol
fMAX tPLH tPHL
TA = -40C to +85C, CL = 50pF Min.
125
Parameter
Maximum Clock Frequency Propagation Delay, CP to Qn Propagation Delay, CP to Qn
VCC (V)(8)
5.0 5.0 5.0
Min.
140 3.0 3.5
Typ.
175 6.5 7.0
Max.
Max.
Units
MHz
9.0 10.0
2.5 2.5
10.0 11.0
ns ns
Note: 8. Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements for ACT
TA = +25C, CL = 50pF Symbol
tS tH tS tH tW
TA = -40C to +85C, CL = 50pF Guaranteed Minimum Units
ns ns ns ns ns 5.5 1.0 5.5 1.0 4.5
Parameter
Setup Time, HIGH or LOW, Dn to CP Hold Time, HIGH or LOW, Dn to CP Setup Time, HIGH or LOW, CE to CP Hold Time, HIGH or LOW, CE to CP CP Pulse Width, HIGH or LOW
VCC (V)(9)
5.0 5.0 5.0 5.0 5.0
Typ.
2.5 -1.0 2.5 -1.0 2.0 4.5 1.0 4.5 1.0 4.0
Note: 9. Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
CIN CPD
Parameter
Input Capacitance Power Dissipation Capacitance
Conditions
VCC = OPEN VCC = 5.0V
Typ.
4.5 90.0
Units
pF pF
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 8
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
Physical Dimensions
13.00 12.60 11.43
20 B 11 A
9.50 10.65 7.60 10.00 7.40 2.25
1 PIN ONE INDICATOR
0.51 0.35
0.25
M
10
1.27
CBA
1.27
0.65
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
C
0.33 0.20
0.10 C SEATING PLANE
0.75 0.25 (R0.10) (R0.10)
8 0
X 45
0.30 0.10
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE PLANE
0.25 1.27 0.40 (1.40)
A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P1030X265-20L F) DRAWING FILENAME: MKT-M20BREV3
SEATING PLANE
DETAIL A
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 9
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 10
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 11
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
Physical Dimensions (Continued)
26.92 24.89
PIN #1
7.11 6.09
(0.97)
1.78 1.14
7 TYP
3.43 3.17 5.33 MAX
7 TYP
7.87
2.54 0.36 0.56
.001[.025] C
3.55 3.17 0.38 MIN
7.62 10.92 MAX 0.20 0.35
NOTES:
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 12
74AC377, 74ACT377 -- Octal D-Type Flip-Flop with Clock Enable
TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. PDP-SPMTM SyncFETTM (R) Power220(R) (R) Power247 The Power Franchise(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) TinyBoostTM Programmable Active DroopTM TinyBuckTM (R) QFET TinyLogic(R) QSTM TINYOPTOTM QT OptoelectronicsTM TinyPowerTM (R) Quiet SeriesTM TinyPWMTM RapidConfigureTM TinyWireTM Fairchild(R) SMART STARTTM Fairchild Semiconductor(R) SerDesTM (R) SPM FACT Quiet SeriesTM UHC(R) STEALTHTM FACT(R) Ultra FRFETTM SuperFETTM FAST(R) UniFETTM SuperSOTTM-3 FastvCoreTM VCXTM (R) (R)* SuperSOTTM-6 FlashWriter SuperSOTTM-8 * EZSWITCHTM and FlashWriter(R) are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPSTM FRFET(R) Global Power ResourceSM Green FPSTM Green FPSTM e-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM MillerDriveTM Motion-SPMTM OPTOLOGIC(R) OPTOPLANAR(R) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.
Rev. I32
ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) EZSWITCHTM * TM
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
(c)1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com 13

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